Methods for forming and integrated circuit structures containing enhanced-surface-area conductive layers

ABSTRACT

An enhanced-surface-area conductive layer compatible with high-dielectric constant materials is created by forming a film or layer having at least two phases, at least one of which is electrically conductive. The film may be formed in any convenient manner, such as by chemical vapor deposition techniques, which may be followed by an anneal to better define and/or crystallize the at least two phases. The film may be formed over an underlying conductive layer. At least one of the at least two phases is selectively removed from the film, such as by an etch process that preferentially etches at least one of the at least two phases so as to leave at least a portion of the electrically conductive phase. Ruthenium and ruthenium oxide, both conductive, may be used for the two or more phases. Iridium and its oxide, rhodium and its oxide, and platinum and platinum-rhodium may also be used. A wet etchant comprising ceric ammonium nitrate and acetic acid may be used. In the case of this etchant and a ruthenium/ruthenium oxide film, the etchant preferentially removes the ruthenium phase, leaving a pitted or “islanded” surface of ruthenium oxide physically and electrically connected by the underlying conductive layer. The remaining pitted or islanded layer, together with the underlying conductive layer, if any, constitutes an enhanced-surface-area conductive layer. The enhanced-surface-area conductive layer may be used to form a plate of a storage capacitor in an integrated circuit, such as in a memory cell of a DRAM or the like.

FIELD OF THE INVENTION

[0001] This invention relates to semiconductor devices and thefabrication thereof, and particularly to ruthenium-containing conductivelayers and the formation and use thereof.

BACKGROUND OF THE INVENTION

[0002] A capacitor generally includes two electrical conductors in closeproximity to, but separated from, each other. The two conductors formthe “plates” of the capacitor, and may be separated by a dielectricmaterial. When a voltage is applied across the plates of a capacitor,electrical charge accumulates on the plates. If the plates areelectrically isolated essentially immediately after a voltage isapplied, the accumulated charge may be stored on the plates, thus“storing” the applied voltage difference.

[0003] The fabrication of integrated circuits involves the formation ofconductive layers for use as various circuit components, including foruse as capacitor plates. Memory circuits, such as DRAMs the like, useconductive layers to form the opposing plates of storage cellcapacitors.

[0004] The drive for higher-performance, lower-cost integrated circuitsdictates ever-decreasing area for individual circuit features, includingstorage capacitors. Since capacitance of a capacitor (the amount ofcharge that can be stored as a function of applied voltage) generallyvaries with the area of capacitor plates, as the circuit area occupiedby the storage capacitor decreases, it is desirable to take steps topreserve or increase capacitance despite the smaller occupied area, sothat circuit function is not compromised.

[0005] Various steps may be taken to increase or preserve capacitancewithout increasing the occupied area. For example, material(s) havinghigher dielectric constant may be used between the capacitor plates.Further, the plate surfaces may be roughened to increase the effectivesurface area of the plates without increasing the area occupied by hecapacitor.

[0006] One method for providing a roughened surface for a plate of astorage cell capacitor is to form the plate of hemispherical grainpolysilicon (HSG), possibly with an overlying metal layer. Thehemispherical grains of HSG enhance the surface area of the platewithout increasing its occupied area.

[0007] HSG presents difficulties in fabrication, however, because of theformation of silicon dioxide on and near the HSG. A silicon dioxidelayer may form on the HSG, particularly during deposition of thecapacitor's dielectric layer. Even with an intervening metal layerpresent, oxygen from the deposition of the dielectric layer can diffusethrough the metal layer, forming silicon dioxide at the polysiliconsurface. Silicon diffusion through the metal layer may also produce asilicon dioxide layer between the metal and the dielectric layers.

[0008] Silicon dioxide between the metal layer and the HSG can degradethe electrical contact to the metal capacitor plate surface. Silicondioxide between the metal layer and the dielectric layer can decreasethe capacitance of the resulting capacitor.

[0009] To attempt to avoid these negative effects caused by formation ofsilicon dioxide, a diffusion barrier layer may be employed between theHSG and the metal layer. But in the typical capacitor geometry, thegreater the total number of layers, the larger the required minimum areaoccupied by the capacitor. Further, the upper surface of each additionallayer deposited over the HSG tends to be smoother than the underlyingsurface, reducing the increased surface area provided by the HSG.

SUMMARY

[0010] The present invention provides an enhanced-surface-area(rough-surfaced) conductive layer compatible with high-dielectricconstant materials and useful in the formation of integrated circuits,particularly for plates of storage capacitors in memory cells.

[0011] The enhanced-surface-area conductive layer may be formed by firstforming a film having two or more phases, such as iridium and iridiumoxide phases, ruthenium and ruthenium oxide phases, rhodium and rhodiumoxide phases, platinum and platinum-rhodium phases, and the like. Thefilm may be formed over an underlying conductive layer. At least one ofthe phases in the film is then selectively removed from the film,leaving at least one of the phases behind to form anenhanced-surface-area conductive layer.

[0012] In an illustrated embodiment, a phase of a layer is removed toleave a pitted surface of a non-removed phase. The pitted surface mayinclude islands formed of the non-removed phase. An “islanded” surfacemay also be formed by the differential removal, the surface of which mayinclude some pits. Any suitable selective removal process may beemployed, such as an etch process or etchant, wet or dry, that etchesone phase at a much greater rate than an other phase. Thermal andelectrochemical selective removal techniques may also be employed. Theselective removal process preferentially removes the one phase, leavinga pitted or “islanded” surface of the other phase. In the case of anislanded surface having separate or isolated islands, an underlyingconductive layer may physically and electrically connect the islands.The layer of remaining pitted or islanded material, together with theunderlying conductive layer, if any, constitutes anenhanced-surface-area electrically conductive layer.

[0013] The enhanced-surface-area conductive layer may be used to form aplate of a storage capacitor in an integrated circuit, such as in amemory cell of a DRAM or the like. If the material chosen to form theenhanced-surface-area conductive layer is relatively resistant tooxidation-induced decreases in conductivity, such as with rutheniumoxide or other oxygen-containing conductors, for example, then thetendency toward silicon dioxide formation may be reduced or eliminated,providing improved compatibility for use with high-dielectric-constantdielectric materials. An intervening metal layer and/or barrier such asused in the HSG approach may also be used, but is desirably omitted fromthe capacitor structure, allowing smaller dimensions for capacitors withthe same or even greater capacitance. This allows the design andfabrication of higher speed, higher density, and lower cost memorycircuits.

BRIEF DESCRIPTION OF THE DRAWINGS

[0014]FIG. 1 is a cross-section of a structure with layers used in anexample of a process according to one embodiment of the presentinvention.

[0015]FIG. 2 is a cross-section of the layers of FIG. 1 after separationor crystallization of separate phases within one of the layers.

[0016]FIG. 3 is a cross-section of the layers of FIG. 2 afterpreferential removal of one of the phases.

[0017]FIG. 4 is a cross section of the layers of FIG. 3 after formationof a dielectric layer on the structure.

[0018]FIG. 5 is a cross section of the layers of FIG. 4 after depositionof a conductive layer on the structure.

[0019]FIG. 6 is a cross-section of a container capacitor structureproduced by a process of the present invention and included in anintegrated circuit.

[0020]FIG. 7 is a computer generated plot of an X-ray diffraction studyof a ruthenium-containing film both before and after preferentialremoval of ruthenium.

DETAILED DESCRIPTION

[0021] The present invention allows the creation of asurface-area-enhanced conductive layer that has improved compatibilitywith high-dielectric-constant (“high-K”) dielectric materials.

[0022] This is achieved by forming a layer of material having at leasttwo phases, at least one of phase of which is a conductive material. Thelayer may be formed over an underlying conductive layer. The layer mayhave two or more phases in an as-deposited state. The layer may also betreated in physical and/or chemical environments, after or duringdeposition, which environments enhance, control, or influence thedevelopment of zones of different phases within the layer.

[0023] After the layer having at least two phases is formed, at leastone of the phases is selectively removed, leaving at least one of thephases of a conductive material behind. The remaining conductive phaseor phases form, together with the underlying conductive layer, if any,an enhanced-surface area conductive layer which may be used to form aplate of a storage capacitor in an integrated circuit, such as in amemory cell of a DRAM or the like. If the material chosen to form theenhanced-surface-area conductive layer is relatively resistant tooxidation-induced decreases in conductivity, as with anoxygen-containing conductor such as ruthenium oxide, for example, thenthe tendency toward silicon dioxide formation may be reduced oreliminated, providing improved compatibility for use withhigh-dielectric-constant dielectric materials.

EXAMPLE EMBODIMENTS

[0024] In accordance with a specific embodiment of the presentinvention, a surface-area-enhanced conductive layer may be created bydifferentially removing ruthenium relative to ruthenium oxide from afilm or layer containing both ruthenium (Ru) and ruthenium oxide (RuO₂)phases. The differential removal process, in this example, may involvethe preferential removal of ruthenium relative to ruthenium oxide in thelayer. For example, the removal may be performed with an etchant and/oretch process that preferentially etches ruthenium relative to rutheniumoxide, leaving an enhanced-surface area layer comprising rutheniumoxide.

[0025] The surface-area-enhanced conductive layer may be formed on asupporting structure 10 shown in partial cross-section in FIG. 1. Thesupporting structure may be any structure present in or on an integratedcircuit during the fabrication thereof, but is typically a conductivematerial that will be in electrical contact with a capacitor plateformed by the surface-area-enhanced conductive layer.

[0026] An underlying electrically conductive layer 12 may be formed ordeposited first onto the structure 10, such as by chemical vapordeposition (CVD), sputtering, or another suitable process. The layer 12is typically of a thickness at least sufficient to maintain continuityof the layer 12, such as at least about 100 Angstroms. The layer 12 maybe formed of any suitable electrically conductive material, but isdesirably formed of ruthenium oxide.

[0027] An oxygen-deficient non-stoichiometric ruthenium oxide (RuO_(x))layer 14 may then be deposited or formed, also by CVD, sputtering, orany other suitable process. In representative examples, the thickness ofthe resulting RuO_(x) layer 14 is between about 1 Angstrom and 500Angstroms. The RuOx layer 14 may then be annealed to facilitatecrystallization of a ruthenium phase and a ruthenium oxide (RuO₂) phaseand/or a non-stoichiometric ruthenium oxide (RuO_(x)) phase within thelayer 14. Annealing may be accomplished, for example, by rapid thermalanneal (RTA) in non-oxidizing ambients, such as nitrogen, ammonia,helium, argon, or by other suitable annealing processes, to produce bothzones 18 of ruthenium (Ru) and zones 16 of ruthenium oxide (RuO₂ and/orRuO_(x)) within the layer 14, as shown in FIG. 2. The gas ratios of theruthenium and oxygen source gases during deposition of the layer 14 maybe selected to create a desired ratio between the amounts of therespective phases present in the layer 14. The deposition conditions andthe RTA time, temperature, and pressure may be selected to provide adesired mean size for the ruthenium zones. The ruthenium zones 18, forexample, desirably extend completely through the thickness of the layer14, as shown, and desirably have a mean diameter of about one to threetimes the thickness of the layer 14 most desirably about two times thethickness of the layer 14, or about 400 Angstroms for a 200-Angstromlayer 14.

[0028] The layer 14 having both ruthenium zones 18 and ruthenium oxidezones 16 may then be processed to differentially remove the rutheniumphase relative to the ruthenium oxide phase, and desirably relative tothe underlying conductive layer 12. In the illustrated embodiment,ruthenium is preferentially removed relative to ruthenium oxide. A wetetch process is one suitable approach for differentially removingruthenium. As a specific example, a wet etchant comprising cericammonium nitrate and acetic acid may be used. Other processes thatremove ruthenium preferentially over ruthenium oxide may also be used.As additional examples, etching using ozonated water or selective dryetch processes may also be employed.

[0029] In the illustrated embodiment, the wet etch process may becontrolled so as to essentially remove the ruthenium phase from thelayer 14, or at least to remove those zones of ruthenium that areexposed to the etch. In the case of ruthenium zones extending completelythrough the layer 14, essentially all of the ruthenium phase may beremoved from the layer 14, as shown in FIG. 3, leaving the rutheniumoxide zones 16.

[0030] Depending on the ratio of ruthenium phase to ruthenium oxidephase in the layer 14, the remaining ruthenium oxide zones 16 may be inthe form of a layer with pits or depressions therein, or in the form ofislands or nodules 20 separated by an open web 22, or a combination ofpits extending partially or entirely through the layer 14 and islands.In other words, the layer 14, following anneal, may comprise arelatively even mixture of ruthenium oxide and ruthenium phases, or itmay be zones of ruthenium phase in a ruthenium oxide matrix, or zones ofruthenium oxide phase in a ruthenium matrix, depending on thecomposition of the pre-annealed layer, and on the anneal conditions.When the layer 14 is subsequently etched in the illustrated example, theenhanced surface-area structure results.

[0031] For a capacitor plate, generally no areas of the plate should beelectrically isolated. The underlying conductive layer 12 thus serves toelectrically connect all of the remaining ruthenium oxide zones 16,particularly if they are in the form of physically separated islands.

[0032] Where the remaining ruthenium oxide is the form of islands, themean distance between nearest edges of such islands is desirably betweenabout three to four times a thickness of a dielectric layer thatconformally covers the layer 14, For example, for a capacitor thatincludes a 60 Angstrom thick tantalum oxide layer, the mean distancebetween the nearest edges of such islands is preferably is in the rangeof 180-240 Angstroms. Where the remaining ruthenium oxide includes pits,the pits have a mean diameter of one to three times the thickness of thelayer 14 and have a mean closest distance that is at least two times thethickness of the layer 14.

[0033] The remaining ruthenium oxide zones 16 shown in FIG. 3constitute, together with the underlying conductive layer 12, anenhanced-surface-area conductive layer compatible withhigh-dielectric-constant dielectric materials. To form a capacitor withthe enhanced-surface-area conductive layer of FIG. 3, a layer 24 of adielectric material is provided on the structure. The layer 24 may be ofa high-dielectric-constant dielectric material, generally any dielectricwith a dielectric constant of at least 9, or more preferably, adielectric constant of at least 20, with tantalum pentoxide (Ta₂O₅)being a specific example. The dielectric material may be formedconformally over the enhanced-surface-area conductive layer, as shown inFIG. 4. Other high-constant dielectrics may also be employed, such asbarium strontium titanium oxide, lead zirconium titanium oxide, andstrontium bismuth tantalum oxide, for example. Because of the relativelylarge diameter of the previously removed ruthenium phase zones, thelayer 24 can conform somewhat to the shape of the enhanced-surface-areaconductive layer, allowing an enhanced surface area on both sides of thelayer 24. In other words, the surface of the layer 24 away from theremaining ruthenium oxide zones is desirably not flat, but follows atleast somewhat the contours of the underlying ruthenium oxide, providingan enhanced surface area on this surface as well.

[0034] A conductive layer 26 may then be formed or deposited conformallyover the dielectric layer 24, as shown in FIG. 5. The surface of layer26 uppermost in the figure is not shown because the layer may generallybe of any thickness sufficiently thick to insure continuity of the layerand sufficiently thin to fit within the overall volume allotted to thecapacitor. As shown in FIG. 5, the surface of layer 26 next to thedielectric layer 24 may conform to the enhanced surface area of thedielectric layer 24, providing an enhanced surface area for theconductive layer 26 as well. The two conductive layers, one formed bylayer 12 and zones 16, and one formed by layer 26, form the two platesof a capacitor. Both plates may have enhanced surface area relative tothe area occupied by the capacitor. The possible omission of anintermediate metal layer and/or barrier layer above the lower plateallows for increased plate surface area and decreased overall thicknessof the capacitor structure.

[0035] Application of the plate structure shown in FIG. 5 to a capacitorof an integrated circuit—a container capacitor in this example—isillustrated in the cross-section of FIG. 6. The supporting structure 10in this example is a conductive plug of polysilicon or other conductivematerial formed at the bottom of an opening in a dielectric material 28such as borophosphosilica glass (BPSG). The plug contacts a circuitelement such as a transistor gate (not shown). At the sides of thecylindrical container, the BPSG itself functions a supporting structurefor the capacitor plate structure. The thinness of the capacitorstructure provided by the layer structure of FIG. 5 maximizes thecapacitor plate surface area in the container capacitor of FIG. 6,particularly for the inner (upper) electrode, the surface area of whichdecreases with increasing thickness of the layer structure. Theenhanced-surface-area layers also increase the effective surface areabeyond that of the occupied area. The use of the enhanced-surface-arearuthenium oxide conductive layer thus provides improved capacitance in agiven area.

[0036]FIG. 7 shows X-ray diffraction data confirming the formation ofruthenium and ruthenium oxide phases as described in this exampleembodiment, with preferential removal of ruthenium. Deposited RuO_(x)films were wet etched in CR14, a well-known commercially available wetetchant comprising ceric ammonium nitrate and acetic acid. Some filmswere annealed in non-oxidizing ambients (for example, N₂, NH₃, He, Ar)prior to the wet etch. SEM examination of annealed films wet-etched inCR14 for 30 seconds showed pitting of the films consistent withpreferential etching of ruthenium, leaving ruthenium oxide, whilenon-annealed films showed less evidence of selective etching. X-raydiffraction studies confirmed the presence of ruthenium and rutheniumoxide in the pre-etch annealed films, and the absence of ruthenium inthe post-etch films. FIG. 7 shows the pre-etch and post-etch X-raydiffraction data, with ruthenium peaks present in a pre-etch trace 701but absent in a post-etch trace 703.

[0037] The invention above is described in detail by means of a specificexample embodiment, but is not limited thereto. Furthermore, variationswithin the scope and spirit of the invention discussed above will beapparent to those of skill in the art. For example, in addition to thefirst layer, the dielectric layer and the overlaying conductive layermay be proximate to one another, with other intervening layers, althoughin the desirable approach, these layers abut one another, and layers 24and 26 need not be homogeneous as they may be formed of multiple layersor materials. The invention is accordingly defined not by the particularembodiments and variations explicitly described, but by the claimsbelow.

We claim:
 1. A method of forming an enhanced-surface-area conductivestructure in the manufacture of a structure for use in an integratedcircuit, the method comprising: forming a layer containing at least twophases, the phases including at least one conductive phase; andpreferentially removing at least one of the at least two phases so as toleave behind at least the at least one conductive phase.
 2. The methodaccording to claim 1, wherein the act of removing comprises etching thelayer.
 3. The method of claim 1, wherein the act of forming comprisesdepositing the layer and annealing the layer.
 4. The method of claim 1,wherein the act of forming comprises forming a layer having phases ofruthenium and of ruthenium oxide.
 5. The method of claim 1, wherein theact of forming comprises depositing a layer of ruthenium oxide andannealing the layer of ruthenium oxide so as to form ruthenium andruthenium oxide phases within the layer.
 6. A method of forming astructure on an integrated circuit, the method comprising: annealing alayer comprising oxygen-deficient non-stoichiometric conductive metallicoxide; and removing metal from the annealed layer at a rate which isgreater than the rate at which metallic oxide is removed from the layer.7. The method of claim 6, wherein the act of annealing comprisesannealing a layer comprising oxygen-deficient non-stoichiometricruthenium oxide.
 8. A method of forming a structure on an integratedcircuit comprising: at least partially separating a first layer intorespective phases; and differentially removing a first phase of therespective phases from the first layer, leaving a second phase of therespective phases within the first layer, wherein the second phase is anelectrically conductive material.
 9. The method according to claim 8,comprising: providing a second layer of a dielectric material inproximity to the first layer; and providing a third electricallyconductive layer in proximity to the second layer.
 10. The methodaccording to claim 9, comprising abutting the first, second, and thirdlayers against one another with no intermediate layers.
 11. The methodaccording to claim 8 in which the act of at least partially separatingthe first layer into respective phases comprises at least partiallyseparating the first layer into respective ruthenium and ruthenium oxidephases.
 12. A method of forming a conductive structure, comprising:forming a layer of electrically conductive material; forming a layer ofnon-stoichiometric ruthenium oxide on the layer of conductive material;annealing the layer of non-stoichiometric ruthenium oxide to formruthenium and ruthenium oxide phases; and differentially removing theruthenium phase relative to the ruthenium oxide phase.
 13. The method ofclaim 12, wherein the non-stoichiometric ruthenium oxide layer isoxygen-deficient.
 14. A method of forming a conductive structure, themethod comprising: depositing a layer of oxygen-deficientnon-stoichiometric ruthenium oxide; annealing the deposited layer for atime and at a temperature sufficient to cause at least some separationof ruthenium and ruthenium oxide phases within the layer; and removingruthenium preferentially over ruthenium oxide from the layer.
 15. Themethod of claim 14, wherein the act of annealing comprises forming zonesof ruthenium phase material within the layer with at least some of thezones extending through an entire thickness of the layer.
 16. The methodof claim 14, wherein the act of annealing comprises forming zones ofruthenium phase material within the layer, wherein a mean diameter ofsuch zones is in the range of about one to about three times a thicknessof the layer.
 17. A method of forming a conductive structure, the methodcomprising: forming a layer of electrically conductive material; forminga layer of oxygen-deficient ruthenium oxide on the layer of conductivematerial; annealing the layer of oxygen-deficient ruthenium oxide toform ruthenium and ruthenium oxide phases; and differentially removingthe ruthenium relative to the ruthenium oxide.
 18. The method of claim17, wherein the act of forming a layer of oxygen-deficient rutheniumoxide comprises depositing a layer of ruthenium oxide.
 19. The method ofclaim 17, wherein the act of differentially removing comprisespreferentially etching a ruthenium phase in a layer of oxygen-deficientruthenium oxide and ruthenium.
 20. A method of forming at least onecapacitor in an integrated circuit, the method comprising: forming afirst conductive layer comprising ruthenium and ruthenium oxide phases;removing ruthenium from the first conductive layer so as to leaveremaining zones of ruthenium oxide; forming a dielectric layer on or inproximity to the remaining zones of ruthenium oxide; and forming asecond conductive layer on or in proximity to the dielectric layer. 21.The method of claim 20, wherein the dielectric layer and secondconductive layer are each a single layer of a homogenous material. 22.The method of claim 20, wherein the act of forming the dielectric layercomprises forming a layer of a material having a dielectric constant ofat least
 9. 23. The method of claim 20, wherein the act of forming thedielectric layer comprises forming a layer of a material having adielectric constant of at least
 20. 24. The method of claim 20, whereinthe act of forming the dielectric layer comprises forming a layer oftantalum pentoxide.
 25. A method of forming a capacitor, comprising:forming a first layer of conductive material; forming a second layerover the first layer of conductive material, the second layer comprisingzones of ruthenium and ruthenium oxide; etching the zones of rutheniumso as to allow the zones of ruthenium oxide to remain; forming a layerof dielectric material on the remaining zones of ruthenium oxide and thefirst layer of conductive material; and forming a third layer ofconductive material on the layer of dielectric material.
 26. The methodof claim 25, wherein the act of forming a first layer comprises forminga first layer of conductive material resistant to the etching performedin the act of etching the zones of ruthenium.
 27. The method of claim25, wherein the act of forming the second layer comprises forming alayer of ruthenium oxide and at least partially separating the layer ofruthenium oxide into ruthenium oxide and ruthenium phases.
 28. Themethod of claim 25, wherein the step of forming a layer of dielectricmaterial comprises forming a layer of dielectric material conformallyover the remaining zones of ruthenium oxide such that a surface of thelayer of dielectric material spaced from the surface of the remainingzones of ruthenium oxide conforms at least in part to the contours ofthe surface of the remaining ruthenium oxide.
 29. The method of claim25, further comprising etching the zones of the ruthenium and rutheniumoxide to have a mean closest distance that is at least twice a thicknessof the layer of dielectric material.
 30. An enhanced-surface-areaconductive structure in an integrated circuit, the structure comprisinga layer of ruthenium oxide having at least one pitted surface.
 31. Acapacitor structure in an integrated circuit, the structure comprising alayer of conductive metallic oxide having a pitted surface with a layerof dielectric material disposed conformally on the pitted surface. 32.The capacitor structure of claim 31, further comprising a layer ofconductive material disposed on the layer of dielectric material. 33.The capacitor structure of claim 31, wherein at least some of the pitsin the surface of the conductive metallic oxide layer extend completelythrough the conductive metallic oxide layer.
 34. The capacitor structureof claim 33, wherein the pits in the surface of the conductive metallicoxide layer have a mean diameter in the range of one to three times athickness of the conductive metallic oxide layer.
 35. The capacitorstructure of claim 33, wherein the pits in the surface have a meanclosest distance that is at least two times a thickness of the layer ofdielectric material.
 36. The capacitor structure of claim 31, whereinthe conductive metallic oxide layer comprises ruthenium oxide.
 37. Aconductive structure in an integrated circuit, the structure comprisinga layer of conductive material with islands of conductive metallic oxidedisposed thereon.
 38. The structure of claim 37, wherein the conductivemetallic oxide comprises ruthenium oxide.
 39. A capacitor structure inan integrated circuit, the structure comprising: a layer of conductivematerial with islands of conductive metallic oxide disposed thereon; anda layer of dielectric material disposed conformally on the islands ofconductive metallic oxide, wherein a portion of a surface of the layerof conductive material is exposed between the islands.
 40. The capacitorstructure of claim 39, wherein the conductive metallic oxide comprisesruthenium oxide.
 41. The capacitor structure of claim 39, furthercomprising a layer of conductive material disposed conformally on thelayer of dielectric material.
 42. An integrated circuit, comprising aplurality of capacitors that include a layer of conductive metallicoxide having a pitted surface with a layer of dielectric materialdisposed conformally on the pitted surface.